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24bit Clockless Link™ 接收器_BU17102AKV-M

BU17102AKV-M是采用罗姆独创的CDR(Clock Data Recovery)方式且实现了低功耗和低EMI化的差分串行接口LSI。通过与BU17101AKV-M进行连接,可将24位CMOS级信号串行化,用1对差分线路进行传输。发射器和接收器之间只有差分线路,没有来自接收器的返回路径。无需复位线路及链接同步控制线路,自动建立链接连接。

型号
Status
封装
包装数量
最小独立包装数量
包装形态
RoHS
BU17102AKV-ME2 供应中 VQFP48 1500 1500 Taping Yes
 
特性:
Sub Family Clockless Link SerDes
Function Deserializer
Input Signal Type Clockless Link
Output Signal Type LVCMOS
No.of Rx 1
Clock frequency (Min.)[MHz] 30
Clock frequency (Max.)[MHz] 51
Clockless Transfer Rates [Gbps] 1.63
Parallel Bus Width 24
Supply Voltage(Min.)[V] 2.3
Supply Voltage(Max.)[V] 3.6
Operating Temperature (Min.)[°C] -40
Operating Temperature (Max.)[°C] 85
特点:
    • High-speed differential serial interface (Maximum 1.6Gbps)
    • Embedded clock interface
    • No lock condition signal and no reset signal between transmitter and receiver. (Only differential signals)
    • Low EMI transmission by original DC balance protocol and scrambling.
    • Selectable 2 modes of CMOS parallel output current.
 
 
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技术信息
Application Note

Thermal Resistance