特点：・24bits data of parallel LVCMOS level inputs are converted to 4 channels of LVDS data stream.
・Support clock frequency from 20MHz up to 112MHz.
・Low power 1.8V CMOS design.
・Power down mode.
・Clock edge selectable.
・Support 6bit/8bit mode selectable.
・Support reduced swing LVDS for low EMI.
・Support LVDS Outputs pin reverse function.
・Support spread spectrum clock generator.
・48pin BGA Package(4mm×4mm ,0.5mm pitch )